1. Field of the Invention
The present invention relates generally to semiconductor dynamic RAMs, and more particularly, to refresh operation of block partitioned semiconductor dynamic RAMs.
2. Description of the Prior Art
In recent years, as a semiconductor dynamic RAM (referred to as DRAM hereinafter), many block partitioned DRAMs have been developed to direct larger capacity of the memory as well as smaller power consumption at the time of operating the memory.
FIG. 1 is a block diagram showing a conventional block partitioned MOS (metal oxide semiconductor) type DRAM.
In FIG. 1, partitioned memory cell arrays 8a and 8b are provided with row decoder 6a and 6b and sense amplifier and I/O controls 9a and 9b, respectively. In addition, the memory cell arrays 8a and 8b are provided with a common column decoder 10. The memory cell arrays 8a and 8b include memory cells (not shown) arranged in a plurality of rows and columns, respectively. Address signals A.sub.0 to A.sub.8 are applied to a row address buffer 2 and a column address buffer 3 through an address input portion 1. The row address buffer 2 generates row address signals RA.sub.0 to RA.sub.8. The column address buffer 3 generates column address signals CA.sub.1 to CA.sub.8. A word line driving signal generating circuit 5 is responsive to the row address signals for generating a word line driving signal through a decode signal generating circuit 4. On this occasion, either one of the memory cell arrays 8a and 8b is selected depending on whether the row address signal RA.sub.0 is "1" or "0". More specifically, the row address signals RA.sub.1 to RA.sub.8 are applied to only either one of the row decoders 6a and 6b depending on the value of the row address signal RA.sub.0. The selected row decoder is responsive to the row address signals RA.sub.1 to RA.sub.8 for selecting one row of the memory cells in the selected memory cell array. Only a sense amplifier and I/O control provided in the selected memory cell array is activated in response to an activating signal from a sense amplifier activating signal generating circuit 7. The column decoder 10 is responsive to the column address signals CA.sub.1 to CA.sub.8 for selecting one column of the memory cells in each of the memory cell arrays 8a and 8b. Thus, information read out from a memory cell determined by a row and a column specified by the row decoder and the column decoder is sensed and amplified by the sense amplifier and I/O control and then, the information is provided to the exterior through a data output buffer 16. The foregoing is the outline of an operation for reading out information. An operation for writing information is basically the same. In this case, information through a data input buffer 18 is written to a specified memory cell in the selected memory cell array.
Thus, in the partitioned memory cell arrays, a sense amplifier provided in a non-selected memory cell array is not activated at the time of a read/write operation of the DRAM, so that the power consumption of the entire DRAM is decreased, as compared with the capacity thereof.
On the other hand, the DRAM is similar in structure of memory cells and suitable for high integration density, as compared with an SRAM (static semiconductor memory device). However, the DRAM uses the principle of storing information charges in a capacitor formed on a semiconductor substrate, so that stored charges are lost with time due to leakage which occurs in a junction between the capacitor and the substrate, or the like. Thus, the DRAM requires a refresh operation for rewriting the stored information every constant time period in order to hold memory. It is the same with a DRAM having partitioned memory cell arrays.
FIG. 2 is a diagram showing specific circuit structure of a portion of one column in each of the memory cell arrays shown in FIG. 1.
In FIG. 2, a plurality of word lines WL.sub.0, WL.sub.1, . . . are arranged intersecting with a bit line pair BL and BL. A memory cell is provided at an intersection of each bit line BL or BL and each word line WL.sub.0, WL.sub.1, . . . . In FIG. 2, only two memory cells connected to the two word lines WL.sub.0 and WL.sub.1 and the bit line pair BL and BL are typically shown. The memory cells comprise a set of MOS transistor T.sub.6 and capacitor C.sub.1 and a set of MOS transistor T.sub.7 and capacitor C.sub.2, respectively. The bit lines BL and BL are connected to a precharge power supply V.sub.BL through MOS transistors T.sub.1 and T.sub.2, respectively. In addition, the bit lines BL and BL are connected to each other through an MOS transistor T.sub.3. The MOS transistors T.sub.1, T.sub.2 and T.sub.3 have their gates connected to a precharging (equalize) signal .phi..sub.pre. Furthermore, the bit lines BL and BL are connected to a sense amplifier 20 for sensing and amplifying stored charges. The sense amplifier 20 is connected to a ground potential V.sub.SS and a power-supply voltage V.sub.CC through MOS transistors T.sub.8 and T.sub.9, respectively. The transistors T.sub.8 and T.sub.9 have their gates connected to sense amplifier activating signals S and S, respectively. Additionally, the bit lines BL and BL are connected to data input/output lines I/O and I/O through MOS transistors T.sub.4 and T.sub.5, respectively. The transistors T.sub.4 and T.sub.5 have their gates connected to a column decoder 10.
FIG. 3 is a timing chart showing generating timing of each signal at the time of an automatic refresh operation of the DRAM shown in FIG. 1.
FIG. 4 is a diagram showing a generating circuit of the sense amplifier activating signal S which is generated in response to a word line driving signal RX shown in FIG. 3. The generating circuit comprises inverters 111 of 2l stages.
Referring now to FIGS. 1 to 3, the refresh operation of the conventional DRAM will be described. Description is now made on a refresh operation based on a CAS before RAS automatic refresh mode which is a recent trend in the refresh operation. An RAS (Row Address Strobe) is a timing signal for accepting the address signals for the row decoder. A CAS (Column Address Strobe) is a timing signal for accepting the address signals for the column decoder. Such signals are provided to accept the row address signals and the column address signals from the same pin in the DRAM having high integration density. More specifically, respective timing for accepting the row address signals and the column address signals in response to the RAS signal and the CAS signal are made different. In addition, various timing signals used in the DRAM are generated in response to the signals, so that timing of the entire circuit is controlled.
When the external CAS signal falls before the external RAS signal (CAS before RAS), a refresh signal REF attains a high level (referred to as "H" level hereinafter) in synchronization with the fall of the external RAS signal, so that the refresh signal REF is applied to a sense restore control circuit 12 from a clock generator 14. The sense restore control circuit 12 is responsive to the level of the REF signal for determining whether the DRAM is in a refresh mode or a normal operation (read/write) mode. The sense restore control circuit 12, which received the signal REF of the "H" level, determines that the DRAM is in the refresh mode, to apply a control signal RNC to the decode signal generating circuit 4. The decode signal generating circuit 4, which received the RNC signal, does not select address information inputted from the row address buffer 2. Alternately, the decode signal generating circuit 4 receives a refresh address outputted from a refresh counter (not shown) included in the sense restore control circuit 12, to use the same as an internal address selecting signal of the row decoder. On the other hand, the decode signal generating circuit 4 does not select address information applied to the column decoder in the refresh operation in response to the RNC signal also applied to the column address buffer 3, so that a column system is not operated. Either one of decode signals RAi and RAi outputted from the decode signal generating circuit 4 for selecting either one of the memory cell arrays 8a and 8b attains the "H" level in response to the fall of the external RAS signal. In this example, the signal RAi attains the "H" level, so that the memory cell array 8b is selected, whereby the refresh address is applied to the row decoder 6b as a word line driving signal RX. One of the word lines, for example, the word line WL.sub.0 in the memory cell array 8b is selected in response to the signal RX, to attain the "H" level. Both the bit lines BL and BL are held at a potential of 1/2 V.sub.CC by rendering conductive the precharge power supply V.sub.BL which is the potential of 1/2 V.sub. CC because the precharging signal .phi..sub.pre is at the "H" level during the time other than the operation time. When the word line WL.sub.0 is selected, the transistors T.sub.1, T.sub.2 and T.sub.3 are turned off, so that the potential of the bit line pair BL and BL is rendered electrically floating. Thus, when the word line WL.sub.0 attains the "H" level, the transistor T.sub.6 is turned on, so that charges stored in the capacitor C.sub.1 is read out to the bit line BL, so that the potential of the bit line BL is changed. On the other hand, since the same amplifier activating signal S attains the "H" level (the sense amplifier activating signal S attains the "L" level) after the delay of a predetermined time period from the rise of the signal RX, the power-supply voltage V.sub.CC and the ground potential are connected to the sense amplifier 20, respectively. The each potential of the bit lines BL and BL becomes the power-supply voltage or the ground potential through the sense amplifier 20 in response to the potential difference between the bit lines BL and BL, respectively, so that the potentials thereof are amplified, respectively. Since the word line WL.sub.0 is maintained at the "H" level, the amplified potential of the bit line BL (V.sub.CC or V.sub.SS) is directly stored in the capacitor C.sub.1. Subsequently, the word line WL.sub.0 attains the "L" level so that the transistor T.sub.6 is turned off, and the precharging signal .phi..sub.pre attains the "H" level. The potentials of the bit lines BL and BL are equalized to return to the state before the refresh operation, so that the refresh operation of a single row address is terminated. In the same manner, refresh operations are successively performed in response to row addresses outputted from the refresh counter. When one cycle of the refresh operations in the selected memory cell array 8b is completed, refresh operations in the memory cell array 8a are performed in the same manner in response to the rise of the decode signal RAi. Consequently, all of the memory cells are refreshed.
The conventional DRAM has a constant cycle time of refresh operations irrespective of whether the capacity is large or small. More specifically, the time required for every one refresh cycle is constant. For example, the DRAM of 256K has a cycle time of 256 cycle/4 ms and the DRAM of 1M has a cycle time of 512 cycle/8 ms. As described above, if the refresh operations are not performed within a predetermined time period, the charges stored in the memory cells change, so that the potential difference which appears on the bit line pair can not be correctly sensed by the sense amplifier 20. This problem naturally becomes larger with increasing capacity of the memory cells. The reason is that the larger the capacity of the memory cells becomes, the longer the time required for one cycle of refresh operations becomes, so that a normal read/write operation is restricted. In addition, when the restriction is desired to be decreased, an interval between the refresh operations becomes long. As a result, the object of the refresh operations is not achieved, so that the reliability of the DRAM is decreased.
Japanese Patent Laying-Open Gazette No. 696/1985 by Matsumura entitled "Semiconductor Memory" discloses a DRAM in which a memory cell array is partitioned into a plurality of blocks, where a memory cycle operation and a refresh operation which are different from each other are simultaneously performed in the blocks, to reduce the number of refresh operations.
In addition, Japanese Patent Laying-Open Gazette No. 122994/1986 by Takemae entitled "Dynamic Semiconductor Memory device" discloses a DRAM in which a memory cell array is partitioned into a plurality of blocks, where an access operation and a refresh operation are performed, respectively, and each of the operations is performed on a priority basis when the operations are simultaneously requested in the same block.
These documents describe that an access operation is performed in a selected block and at the same time, a refresh operation is performed in a non-selected block, to reduce the number of refresh operations, thereby to improve the busy rate. However, the documents fail to disclose a method for performing an efficient refresh operation in consideration of only the refresh operation, unlike the present invention.